/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.

All rights reserved.

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are permitted provided that the following conditions are met:

1. Redistributions of source code must retain the above copyright notice, this 
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2. Redistributions in binary form must reproduce the above copyright notice, 
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.

3. Neither the name of Loongson Technology Corporation Limited nor the names of 
its contributors may be used to endorse or promote products derived from this 
software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
`include "config.h"

module axi_wrap_ddr(
    input         aclk,
    input         aresetn,
    input         xtal_clk,
    input         button_resetn,
    input         ddr_clk_ref,
    output reg    ddr_aresetn,

    //ar
    input  [4 :0] s_axi_arid   ,
    input  [31:0] s_axi_araddr ,
    input  [7 :0] s_axi_arlen  ,
    input  [2 :0] s_axi_arsize ,
    input  [1 :0] s_axi_arburst,
    input         s_axi_arlock ,
    input  [3 :0] s_axi_arcache,
    input  [2 :0] s_axi_arprot ,
    input         s_axi_arvalid,
    output        s_axi_arready,
    //r
    output [4 :0] s_axi_rid    ,
    output [31:0] s_axi_rdata  ,
    output [1 :0] s_axi_rresp  ,
    output        s_axi_rlast  ,
    output        s_axi_rvalid ,
    input         s_axi_rready ,
    //aw
    input  [4 :0] s_axi_awid   ,
    input  [31:0] s_axi_awaddr ,
    input  [7 :0] s_axi_awlen  ,
    input  [2 :0] s_axi_awsize ,
    input  [1 :0] s_axi_awburst,
    input         s_axi_awlock ,
    input  [3 :0] s_axi_awcache,
    input  [2 :0] s_axi_awprot ,
    input         s_axi_awvalid,
    output        s_axi_awready,
    //w
    input  [31:0] s_axi_wdata  ,
    input  [3 :0] s_axi_wstrb  ,
    input         s_axi_wlast  ,
    input         s_axi_wvalid ,
    output        s_axi_wready ,
    //b
    output [4 :0] s_axi_bid    ,
    output [1 :0] s_axi_bresp  ,
    output        s_axi_bvalid ,
    input         s_axi_bready ,

    //-----SDRAM interface------
    output [12:0] dram_addr,
    output [1:0]  dram_ba,
    output        dram_cas_n,
    output        dram_cke,
    output        dram_clk,
    output [1:0]  dram_cs_n,
    output        dram_ras_n,
    output        dram_we_n,
    inout [31:0]  dram_dq,
    output [1:0]  dram_dqml,
    output [1:0]  dram_dqmh

    //------DDR3 interface------
    // inout  [15:0] ddr3_dq,
    // output [12:0] ddr3_addr,
    // output [2 :0] ddr3_ba,
    // output        ddr3_ras_n,
    // output        ddr3_cas_n,
    // output        ddr3_we_n,
    // output        ddr3_odt,
    // output        ddr3_reset_n,
    // output        ddr3_cke,
    // output [1:0]  ddr3_dm,
    // inout  [1:0]  ddr3_dqs_p,
    // inout  [1:0]  ddr3_dqs_n,
    // output        ddr3_ck_p,
    // output        ddr3_ck_n
);

wire init_end;

sdram_new u_sdram (
    .clk(xtal_clk),
    .clk_ref(ddr_clk_ref),
    .rst_n(button_resetn),
    .s_axi_arid(s_axi_arid),
    .s_axi_araddr(s_axi_araddr),
    .s_axi_arlen(s_axi_arlen),
    .s_axi_arsize(s_axi_arsize),
    .s_axi_arburst(s_axi_arburst),
    .s_axi_arlock(s_axi_arlock),
    .s_axi_arcache(s_axi_arcache),
    .s_axi_arprot(s_axi_arprot),
    .s_axi_arvalid(s_axi_arvalid),
    .s_axi_arready(s_axi_arready),
    .s_axi_rid(s_axi_rid),
    .s_axi_rdata(s_axi_rdata),
    .s_axi_rresp(s_axi_rresp),  
    .s_axi_rlast(s_axi_rlast),
    .s_axi_rvalid(s_axi_rvalid),
    .s_axi_rready(s_axi_rready),
    .s_axi_awid(s_axi_awid),
    .s_axi_awaddr(s_axi_awaddr),
    .s_axi_awlen(s_axi_awlen),
    .s_axi_awsize(s_axi_awsize),
    .s_axi_awburst(s_axi_awburst),
    .s_axi_awlock(s_axi_awlock),
    .s_axi_awcache(s_axi_awcache),
    .s_axi_awprot(s_axi_awprot),
    .s_axi_awvalid(s_axi_awvalid),
    .s_axi_awready(s_axi_awready),
    .s_axi_wdata(s_axi_wdata),
    .s_axi_wstrb(s_axi_wstrb),
    .s_axi_wlast(s_axi_wlast),
    .s_axi_wvalid(s_axi_wvalid),
    .s_axi_wready(s_axi_wready),
    .s_axi_bid(s_axi_bid),
    .s_axi_bresp(s_axi_bresp),
    .s_axi_bvalid(s_axi_bvalid),
    .s_axi_bready(s_axi_bready),
    .dram_addr(dram_addr),
    .dram_ba(dram_ba),
    .dram_cas_n(dram_cas_n),
    .dram_cke(dram_cke),
    .dram_clk(dram_clk),
    .dram_cs_n(dram_cs_n),
    .dram_ras_n(dram_ras_n),
    .dram_we_n(dram_we_n),
    .dram_dq(dram_dq),
    .dram_dqml(dram_dqml),
    .dram_dqmh(dram_dqmh),
    .init_end(init_end)
);


always @ (posedge xtal_clk) begin
    ddr_aresetn <= button_resetn && init_end;
end

//ddr axi
//ar
// wire [4 :0] mig_arid   ;
// wire [31:0] mig_araddr ;
// wire [7 :0] mig_arlen  ;
// wire [2 :0] mig_arsize ;
// wire [1 :0] mig_arburst;
// wire        mig_arlock ;
// wire [3 :0] mig_arcache;
// wire [2 :0] mig_arprot ;
// wire        mig_arvalid;
// wire        mig_arready;
// //r
// wire [4 :0] mig_rid    ;
// wire [31:0] mig_rdata  ;
// wire [1 :0] mig_rresp  ;
// wire        mig_rlast  ;
// wire        mig_rvalid ;
// wire        mig_rready ;
// //aw
// wire [4 :0] mig_awid   ;
// wire [31:0] mig_awaddr ;
// wire [7 :0] mig_awlen  ;
// wire [2 :0] mig_awsize ;
// wire [1 :0] mig_awburst;
// wire        mig_awlock ;
// wire [3 :0] mig_awcache;
// wire [2 :0] mig_awprot ;
// wire        mig_awvalid;
// wire        mig_awready;
// //w
// wire [31:0] mig_wdata  ;
// wire [3 :0] mig_wstrb  ;
// wire        mig_wlast  ;
// wire        mig_wvalid ;
// wire        mig_wready ;
// //b
// wire [4 :0] mig_bid    ;
// wire [1 :0] mig_bresp  ;
// wire        mig_bvalid ;
// wire        mig_bready ;

// wire ui_clk;
// wire ui_clk_sync_rst;
// wire init_calib_complete;

// Axi_CDC  u_Axi_CDC_mig (
//     .axiInClk                ( aclk                  ),
//     .axiInRstn               ( aresetn               ),
//     .axiOutClk               ( ui_clk                ),
//     .axiOutRstn              ( ddr_aresetn           ),

//     .axiIn_awvalid           ( s_axi_awvalid         ),
//     .axiIn_awaddr            ( s_axi_awaddr          ),
//     .axiIn_awid              ( s_axi_awid            ),
//     .axiIn_awlen             ( s_axi_awlen           ),
//     .axiIn_awsize            ( s_axi_awsize          ),
//     .axiIn_awburst           ( s_axi_awburst         ),
//     .axiIn_awlock            ( s_axi_awlock          ),
//     .axiIn_awcache           ( s_axi_awcache         ),
//     .axiIn_awprot            ( s_axi_awprot          ),
//     .axiIn_wvalid            ( s_axi_wvalid          ),
//     .axiIn_wdata             ( s_axi_wdata           ),
//     .axiIn_wstrb             ( s_axi_wstrb           ),
//     .axiIn_wlast             ( s_axi_wlast           ),
//     .axiIn_bready            ( s_axi_bready          ),
//     .axiIn_arvalid           ( s_axi_arvalid         ),
//     .axiIn_araddr            ( s_axi_araddr          ),
//     .axiIn_arid              ( s_axi_arid            ),
//     .axiIn_arlen             ( s_axi_arlen           ),
//     .axiIn_arsize            ( s_axi_arsize          ),
//     .axiIn_arburst           ( s_axi_arburst         ),
//     .axiIn_arlock            ( s_axi_arlock          ),
//     .axiIn_arcache           ( s_axi_arcache         ),
//     .axiIn_arprot            ( s_axi_arprot          ),
//     .axiIn_rready            ( s_axi_rready          ),
//     .axiOut_awready          ( mig_awready           ),
//     .axiOut_wready           ( mig_wready            ),
//     .axiOut_bvalid           ( mig_bvalid            ),
//     .axiOut_bid              ( mig_bid               ),
//     .axiOut_bresp            ( mig_bresp             ),
//     .axiOut_arready          ( mig_arready           ),
//     .axiOut_rvalid           ( mig_rvalid            ),
//     .axiOut_rdata            ( mig_rdata             ),
//     .axiOut_rid              ( mig_rid               ),
//     .axiOut_rresp            ( mig_rresp             ),
//     .axiOut_rlast            ( mig_rlast             ),

//     .axiIn_awready           ( s_axi_awready         ),
//     .axiIn_wready            ( s_axi_wready          ),
//     .axiIn_bvalid            ( s_axi_bvalid          ),
//     .axiIn_bid               ( s_axi_bid             ),
//     .axiIn_bresp             ( s_axi_bresp           ),
//     .axiIn_arready           ( s_axi_arready         ),
//     .axiIn_rvalid            ( s_axi_rvalid          ),
//     .axiIn_rdata             ( s_axi_rdata           ),
//     .axiIn_rid               ( s_axi_rid             ),
//     .axiIn_rresp             ( s_axi_rresp           ),
//     .axiIn_rlast             ( s_axi_rlast           ),
//     .axiOut_awvalid          ( mig_awvalid           ),
//     .axiOut_awaddr           ( mig_awaddr            ),
//     .axiOut_awid             ( mig_awid              ),
//     .axiOut_awlen            ( mig_awlen             ),
//     .axiOut_awsize           ( mig_awsize            ),
//     .axiOut_awburst          ( mig_awburst           ),
//     .axiOut_awlock           ( mig_awlock            ),
//     .axiOut_awcache          ( mig_awcache           ),
//     .axiOut_awprot           ( mig_awprot            ),
//     .axiOut_wvalid           ( mig_wvalid            ),
//     .axiOut_wdata            ( mig_wdata             ),
//     .axiOut_wstrb            ( mig_wstrb             ),
//     .axiOut_wlast            ( mig_wlast             ),
//     .axiOut_bready           ( mig_bready            ),
//     .axiOut_arvalid          ( mig_arvalid           ),
//     .axiOut_araddr           ( mig_araddr            ),
//     .axiOut_arid             ( mig_arid              ),
//     .axiOut_arlen            ( mig_arlen             ),
//     .axiOut_arsize           ( mig_arsize            ),
//     .axiOut_arburst          ( mig_arburst           ),
//     .axiOut_arlock           ( mig_arlock            ),
//     .axiOut_arcache          ( mig_arcache           ),
//     .axiOut_arprot           ( mig_arprot            ),
//     .axiOut_rready           ( mig_rready            )
// );

// always @ (posedge ui_clk) begin
//     ddr_aresetn <= ~ui_clk_sync_rst && init_calib_complete;
// end

// //ddr3 controller
// mig_axi_32 mig_axi (
//     // Inouts
//     .ddr3_dq             (ddr3_dq         ),  
//     .ddr3_dqs_p          (ddr3_dqs_p      ),
//     .ddr3_dqs_n          (ddr3_dqs_n      ),
//     // Outputs
//     .ddr3_addr           (ddr3_addr       ),  
//     .ddr3_ba             (ddr3_ba         ),
//     .ddr3_ras_n          (ddr3_ras_n      ),                        
//     .ddr3_cas_n          (ddr3_cas_n      ),
//     .ddr3_we_n           (ddr3_we_n       ),                          
//     .ddr3_reset_n        (ddr3_reset_n    ),
//     .ddr3_ck_p           (ddr3_ck_p       ),                          
//     .ddr3_ck_n           (ddr3_ck_n       ),       
//     .ddr3_cke            (ddr3_cke        ),                          
//     .ddr3_dm             (ddr3_dm         ),
//     .ddr3_odt            (ddr3_odt        ),
    
// 	.ui_clk              (ui_clk          ),
//     .ui_clk_sync_rst     (ui_clk_sync_rst ),
 
//     .sys_clk_i           (xtal_clk        ),
//     .sys_rst             (button_resetn   ),                        
//     .init_calib_complete (init_calib_complete),
//     .clk_ref_i           (ddr_clk_ref     ),
//     .mmcm_locked         (                ),
	
// 	.app_sr_active       (                ),
//     .app_ref_ack         (                ),
//     .app_zq_ack          (                ),
//     .app_sr_req          (1'b0            ),
//     .app_ref_req         (1'b0            ),
//     .app_zq_req          (1'b0            ),
    
//     .aresetn             (ddr_aresetn     ),
//     .s_axi_awid          (mig_awid        ),
//     .s_axi_awaddr        (mig_awaddr[26:0]),
//     .s_axi_awlen         (mig_awlen       ),
//     .s_axi_awsize        (mig_awsize      ),
//     .s_axi_awburst       (mig_awburst     ),
//     .s_axi_awlock        (mig_awlock      ),
//     .s_axi_awcache       (mig_awcache     ),
//     .s_axi_awprot        (mig_awprot      ),
//     .s_axi_awqos         (4'b0            ),
//     .s_axi_awvalid       (mig_awvalid     ),
//     .s_axi_awready       (mig_awready     ),
//     .s_axi_wdata         (mig_wdata       ),
//     .s_axi_wstrb         (mig_wstrb       ),
//     .s_axi_wlast         (mig_wlast       ),
//     .s_axi_wvalid        (mig_wvalid      ),
//     .s_axi_wready        (mig_wready      ),
//     .s_axi_bid           (mig_bid         ),
//     .s_axi_bresp         (mig_bresp       ),
//     .s_axi_bvalid        (mig_bvalid      ),
//     .s_axi_bready        (mig_bready      ),
//     .s_axi_arid          (mig_arid        ),
//     .s_axi_araddr        (mig_araddr[26:0]),
//     .s_axi_arlen         (mig_arlen       ),
//     .s_axi_arsize        (mig_arsize      ),
//     .s_axi_arburst       (mig_arburst     ),
//     .s_axi_arlock        (mig_arlock      ),
//     .s_axi_arcache       (mig_arcache     ),
//     .s_axi_arprot        (mig_arprot      ),
//     .s_axi_arqos         (4'b0            ),
//     .s_axi_arvalid       (mig_arvalid     ),
//     .s_axi_arready       (mig_arready     ),
//     .s_axi_rid           (mig_rid         ),
//     .s_axi_rdata         (mig_rdata       ),
//     .s_axi_rresp         (mig_rresp       ),
//     .s_axi_rlast         (mig_rlast       ),
//     .s_axi_rvalid        (mig_rvalid      ),
//     .s_axi_rready        (mig_rready      )
// );

endmodule
